The latest FPGAs in telecom equipment, servers, and data centers have multiple power rails that need to be properly sequenced to safely power these systems up and down. Designers of high-reliability DC-DC regulators and FPGA power management need an easy way to safely discharge bulk capacitors to avoid damage to the system.

The latest FPGAs in telecom equipment, servers, and data centers have multiple power rails that need to be properly sequenced to safely power these systems up and down. Designers of high-reliability DC-DC regulators and FPGA power management need an easy way to safely discharge bulk capacitors to avoid damage to the system.

FPGA Power Sequencing

The latest in the process of generating system-on-chip FPGAs, they can provide ten independent power rails for Vcores, memory bus power, I/O controllers, Ethernet, and more. As shown in Figure 1, each power rail is powered by DC. The DC converter can regulate the voltage required by 3.3 V, 2.5 V, 1.8 V, 0.9 V, etc. To power up the system, follow a specific sequence to ensure safe operation and avoid damaging the system. Also during system shutdown, the power sequence is reversed, ensuring that each power rail is disabled before the next power rail shuts down. This command is controlled by the power sequencer chip, which enables each DC-DC regulator, as shown in Figure 1.

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 1: A typical FPGA system power rail supplies power to each service.

The problem arises when considering the charge stored in the decoupling capacitors on the various power rails. For example, on a 0.9 V Vcore power rail, the total decoupling capacitance can be on the order of 10 to 20mF, and the residual charge stored in the capacitor bank needs to be actively discharged during a power-down, before the next power-off sequence is disabled. This avoids violating the power-down sequence and protects the FPGA system. Therefore, it is recommended to use an active discharge circuit at each DC-DC regulator output.

Active Capacitor Discharge Switch

By knowing the size of the capacitor bank, the RC time constant can be discharged using an open-ended approach. Once the voltage is less than 95% of the state of charge (which occurs with a 3×RC time constant), the capacitor is assumed to be discharged.

An easy way to do this is through a switch with a known resistance to ground that can be turned on when a discharge is required. Referring to Figure 1, the power sequencer enables the output of each DC-DC regulator. This same enable (EN) signal can then be used to feed switches connected in parallel to the capacitor bank. The switch is driven by inverting the enable signal, which discharges the capacitor when the output of the DC-DC regulator is disabled. For switching, an N-channel power MOSFET is preferred because it is easily driven from a ground-referenced logic signal. The selected circuit is shown in Figure 2, Q2 is an N-channel power MOSFET, and Q1 is a P-channel MOSFET, which reverses the EN logic signal of the power sequencer.

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 2: Active discharge circuit.

Active Capacitor Discharge Circuit Operation

See Figure 2 – The EN output of the power sequencer powers the enable pin on the DC-DC regulator as well as the capacitor discharge circuit. When a logic “0” signals a shutdown, the P-channel MOSFET (Q1) inverts the signal and turns on the N-channel MOSFET (Q2) to discharge the capacitor bank.

The discharge circuit assumes that once the shutdown signal is applied, the DC-DC regulator cannot continue to produce output. If the output of the DC-DC regulator is energized after the shutdown command is activated, a delay must be introduced before the discharge circuit is activated. This is to ensure that the discharge MOSFET is not trying to sink the full output current capability of the DC-DC regulator.

To boost the N-channel power MOSFET (Q2) from a logic “0” signal, the P-channel MOSFET (Q1) inverts the signal to 5 V to apply to the Q2 gate source. The P-channel MOSFET (Q1) is chosen not to have a low gate threshold voltage (VGS(th)). This is because VGS(th) drops relative to temperature and Q1 needs to be in the OFF state during the logic “1” state to avoid false turn-on of Q2. The optimum value for 5 V operation needs to be selected along with the Power Sequencer.

When the power sequencer outputs a logic “1”, the DC-DC regulator is enabled in the ON state and Q2 must be in the OFF state. With a logic “1” output, the minimum high-level output voltage is 4.19 V (EN pin output specification of the power sequencer), then at an ambient operating temperature of 60°C, Q1 VGS(th) needs to be greater than 0.9 V. Additionally, the gate of Q2 needs to be pulled down to the source potential through the 100kΩ R1 resistor to avoid false turn-on.

The change in VGS(th) over temperature is found in a typical electrical curve. MOSFET datasheet. For example, the normalized VGS(th) versus temperature for ZXMP6A13F from Diodes Incorporated is given in Figure 3. The ZXMP6A13F is the device of choice because the guaranteed minimum VGS(th) is 1 V at room temperature and drops at 60°C to about 0.9 V °C.
 

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 3: Temperature-normalized RDS(on) and VGS(th) curves of ZXMP6A13F.

When the power sequencer enable output goes to logic “0”, there is a maximum low level output of 0.270 V, and Q1 needs to ensure that the 5 V – 0.270 V signal boost channel is passed through to ensure that Q2 conducts and discharges the capacitor bank . Therefore, Q1 needs to have an on state at VGS = -4.5 V.

To discharge the capacitor bank, the N-channel power MOSFET (Q2) is selected with an on-resistance (RDS(on)) suitable for discharging the maximum capacitor bank in 10 ms to ensure that 10 is completed in less than 100 ms Complete shutdown sequence for each channel. Auxiliary power must be provided to drive the shutdown circuit (power sequencer) at least 100 ms after the power is turned off.

time of discharge calculation

Use 3 x RC time constant, where R is the combined resistance of the ESR of the capacitor bank (assuming
Safe Operating Area and Transient Thermal Stress

The power rating of power MOSFET Q2 is chosen to handle the transient power dissipation of the discharge current. Calculate the peak power by simulation and check the value against the transient power capacity graph of the power MOSFET datasheet. Since the power MOSFET will dissipate the energy from the capacitor over time as a function of current and voltage, the Safe Operating Area (SOA) curve in the datasheet needs to be checked. This will provide the largest single pulse the power MOSFET can safely handle while ensuring that the junction temperature does not exceed the absolute maximum rating, typical TJ(max) = 150°C. The SOA should be based on the application’s ambient operating temperature and desired MOSFET gate drive, which in this case is 4.5V. With the 0.9 V charged capacitor bank discharged, the SOA curves were then examined for pulse width curves between 1 ms and 10 ms for single-pulse peak current capability at 1 V. The SOA should target the typical application ambient temperature (assuming 60°C) while being mounted on the PCB with minimal heat dissipation, also known as the Minimum Recommended Pad (MRP) layout. Under these conditions, refer to Figure 4 for the SOA of the DMN3027LFG.

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 4: Secure Operating Area (SOA) of the DMN3027LFG

The peak inrush current of the capacitor bank needs to be measured in the actual circuit to ensure sufficient resistance to slow down the response to avoid sharply rising current spikes that can cause EMI issues and transient thermal stress on the N-channel power MOSFET and capacitor bank. In Figure 2, a 50mΩ series resistor is added to the drain of Q2 to ensure that a fixed, known value (independent of temperature) dominates the total resistance in the discharge path.

MOSFET on-resistance variation

Note that the on-resistance of the MOSFET varies with temperature, as shown in Figure 5, by up to 15mΩ over the expected operating temperature range for a 4.5V gate drive. In addition to that, you’ll be doing RDS(on) changes from part to part and from batch to batch. Typical RDS(on) is 22mΩ, with a maximum specification limit of 26mΩ for the 4.5 V gate drive on the DMN3027LFG at room temperature.

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 5: On-resistance temperature response of the DMN3027LFG.

Therefore, to ensure a known resistance dominates the discharge path, the best practice is to use an R2 series resistor that is approximately twice the maximum RDS(on) on the selected gate driver. When R2 is 50mΩ and RDS(on) varies from 15mΩ to 40mΩ (22mΩ typical), the 95% discharge time is 3.9 to 5.4 ms (3 x RC). This is a worst case capacitor bank size of 20 mF.

Power consumption

Calculating the power dissipation of the power MOSFET Q2 and series resistor R2 depends on the duty cycle and the time Q2 is on.

If the 0.9 V output on the DC-DC regulator is enabled while Q2 is on, then 11 W can be reached between Q2 and R2. Assuming a junction temperature of 150°C, a typical RDS(on) settles at 35mΩ, as shown in Figure 5. This should not be allowed as it violates the maximum power dissipation of the DMN3027LFG and causes the junction temperature to exceed the absolute maximum ratings. Therefore, the DC-DC regulator output must be disabled while Q2 is enabled.

This means that the worst case is caused by charging and discharging the capacitor for a short period of time. Assuming the power sequencer goes into a continuous loop enable and then disables the DC-DC regulator every 20 ms (10 ms enable + 10 ms disable), then this will result in about 0.5 W across Q2 and R2. This is achieved by Calculated knowing that the total energy stored in the capacitor bank will be discharged every 20 ms:

P = E/t = ?CV2/20 ms = 500 mW, C = 20 mF for the largest capacitor bank charged to 1 V.

Worst case RDS(on) is 40mΩ, 26mΩx1.5, VGS = 4.5 V, TJ(max) = 150°C (Figure 3). Therefore, the power dissipation of Q2 and R2 is 222 mW and 278 mW, respectively. A minimum RDS(on) of 15mΩ would increase the power dissipation in R2 to 385 mW; meaning a 0.5 W rated surface mount resistor is required.

In a typical application, where the ambient temperature is expected to reach 60°C, the DMN3027LFG has RθJA=130°C/W on the minimum recommended pad layout, and TJ reaches 90°C while dissipating 222mW. This provides ample room for TJ(max) = 150°C.

Capacitor Bank Discharge Measurement

A capacitor bank using 6 x 2,200 uF electrolytic capacitors (13.2 mF) was assembled using the DMN3027LFG and ZXMP6A13F as shown in Figure 2. The ZXMP6A13F was manually triggered with a 5 V signal.

Measurements were made with and without a 50mΩ series resistance, followed by measurements at room temperature, subzero, and high temperature to observe changes in peak current and discharge time. Discharging only through the DMN3027LFG channel RDS(on) resistor (without 50mΩ) produces the worst case where the maximum peak current is observed. Note the different time scales in the curves below – 200 μs/div and 1 ms/div Channel 1 (C1) in yellow = voltage on the gate pin of the DMN3027LFG Channel 3 (C3) in magenta = voltage on the capacitor bank.

Channel 4 (C4) is green = current probe from DMN3027LFG source pin

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 6: Room temperature measurement (approximately Ta = 20°C).

Left Curve = 30 A Peak Current Discharged Through DMN3027LFG Channel Resistor Only (200µs/div) Right Curve = 12.5 Peak Current Discharged Through DMN3027LFG and 50mΩ Series Resistor (1 ms/div) See Figure 6, Figure 7 and Figure 8 – Only through The DMN3027LFG discharges the 13.2 mF capacitor bank, resulting in a peak current that varies from 24 A to 35 A, depending on the temperature response of the MOSFET RDS(on).By adding a 50mΩ series resistor, the peak current can be limited to

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system
Figure 7: High temperature measurement (approximately Ta = 70°C).

Left curve = 24 peak current discharge through DMN3027LFG channel resistor only (200μs/div) Right curve = 11 peak current through DMN3027LFG and 50mΩ series resistor (1 ms/div)

What problems should be paid attention to in the design of active capacitor discharge circuit in FPGA system

Figure 8: Subzero temperature measurement (approximately Ta = -20°C).

Left curve = 35 Peak current discharge through DMN3027LFG channel resistor only (200 μs/div) Right curve = 14 Peak current discharge through DMN3027LFG and 50mΩ series resistor (1 ms/div) Conclusion.

A safe and simple method of discharging large capacitor banks based on known RC time constants has been demonstrated. This open technology can be scaled according to the capacitance size. The following devices were selected:

Q1 = ZXMP6A13F P-Channel MOSFET in SOT23
Q2 = DMN3027LFG N-Channel MOSFET in PowerDI3333-8 R2 = 50mΩ surface mount resistor capable of dissipating 500 mW.
By adding a 50mΩ series resistor in the discharge path, the peak discharge current can be limited and temperature changes can be stabilized. The measured and simulated results are in good agreement; giving the designer the confidence to model different capacitor bank sizes.

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