Non-volatile memory (NVM) plays a key role in almost all embedded system designs, but many designs have more requirements for non-volatile memory in terms of data writing and access speed, data retention, and low power consumption. More stringent. This is especially true in automotive applications, where designers are working hard to create more advanced functions, such as mission-critical functions such as advanced driver assistance systems (ADAS).

In order to ensure the safe and reliable operation of these systems, designers need to study advanced ferroelectric random access memory (F-RAM) as a low power consumption requiring high reliability, low power consumption and faster than current NVM solutions The choice of automotive-grade NVM.

This article discusses the key features of F-RAM technology, and introduces how developers use Cypress semiconductor’s two F-RAM solutions to enhance the reliability of ADAS, and use ADAS as an agent to expand the use of F-RAM to others Mission-critical applications.

Automotive NVM requirements

The automotive industry continues to integrate more advanced sensors with higher resolution and faster update rates, and automotive safety applications are the epitome of this industry trend. The continuous development of automotive subsystems such as ADAS, Electronic control units (ECU) and event data recorders (EDR) is highly dependent on the large amounts of data collected from various sensors. Any loss of data, or even a slowdown in data access speed, may endanger the safety of the system, vehicles and passengers.

For example, in an ADAS design, the time required to write to an electrically erasable programmable read-only memory (EEPROM) can introduce catastrophic delays, resulting in slow response to automatic operations designed to avoid detecting dangerous situations. In the EDR design, if a vehicle accident causes a power failure, the slow writing speed may lead to the loss of key sensor data, making the data needed to understand the root cause of the accident invisible.

F-RAM NVM features

Storage devices constructed with F-RAM technology can effectively replace NVM and meet the increasing demand and performance requirements for reliable data storage and high-speed access. Such devices are made of lead zirconate titanate (Pb[ZrxTi1?x]O3, referred to as PZT). PZT has unique properties. After an electric field is applied, the metal vacancies (cations) embedded in the PZT crystal can obtain one of two possible polarization states (up or down) according to the direction of the electric field (Figure 1).

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 1: F-RAM technology utilizes two equally stable energy states that PZT materials exhibit when subjected to an electric field.

Since both are in a low energy state, when the electric field is removed, the cation will continue to be in its most recent polarization state (Figure 2). When a positive or negative electric field is applied, the cation will quickly transition to the proper polarization state again, following a characteristic hysteresis loop similar to that of ferromagnetic materials.

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 2: PZT material follows a characteristic hysteresis loop and switches between two stable polarization states in response to an applied electric field.

The characteristics of F-RAM technology directly determine the many advantages of NVM devices manufactured using this technology. The two PZT energy states are equally stable, so the cation can remain unchanged in its last position for decades or even hundreds of years, making the PZT-based F-RAM NVM device have an unprecedented data retention period. In addition, this technology is based on cation sites instead of the charge storage mechanism of other NVM technologies, so F-RAM devices have inherent radiation tolerance and are not affected by the single event flip of ionizing radiation.

In addition to the advantages of long-term storage, F-RAM technology also enhances the dynamic performance of NVM devices. State transitions are very rapid and require very little energy, overcoming the fundamental limitations associated with the use of EEPROM or flash memory in mission-critical applications. During relatively slow write cycles, EEPROM and flash memory devices require a considerable “dwell time” (soak TIme) related to data buffering. This extra delay in the write cycle puts the data at risk. If the power fails before the operation is completed and the final read status is checked, the data may be completely lost (Figure 3).

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 3: Compared with F-RAM devices, EEPROM or flash memory write operations require a relatively long dwell time (highlighted in red), during which data is still at risk.

In order to cope with the slower write cycle of EEPROM or flash memory, if developers want to reduce the impact of power failure, they need to add a large capacitor or battery and an appropriate voltage regulator to maintain the NVM power supply voltage for a long enough time to complete the write operation. In contrast, F-RAM (such as Cypress Semiconductor’s Excelon-Auto device) operates at bus speed during write operations, greatly reducing the possibility of critical data loss and eliminating the need for supplementary power in the design.

Automotive grade F-RAM device

Excelon?-Auto F-RAM devices are similar in function to serial EEPROM and serial flash memory, and are designed to meet the needs of mission-critical applications for reliable, high-performance NVM. Automotive system designers can use these AEC-Q100-compliant devices to replace other types of memory; there are two models to choose from: CY15V102QN uses 1.71 to 1.89 V voltage, and CY15B102QN uses 1.8 to 3.6 V voltage. Both are 2 megabit (Mb) devices with a 256 Kb x 8 logical organization structure.

In the operating temperature range of -40°C to +125°C, the data retention period of Excelon F-RAM far exceeds other NVM technologies. For example, CY15x102QN can retain data for approximately 121 years when operating at a temperature of 85°C. The data retention period is inversely proportional to temperature. If it is forced to operate at the higher end of the typical engine temperature (for example, 95°C), the estimated data retention period for F-RAM is 35 years.

In terms of reliability, F-RAM has a read/write cycle endurance of 1013, which is about 7 orders of magnitude higher than typical EEPROM or flash memory. Therefore, developers using such F-RAM devices do not need to implement techniques such as wear leveling (distributing write operations to sectors to solve the problem of limited write cycles in other NVM technologies).

Simplified design using F-RAM

In a typical design, developers can use such devices to directly replace or supplement other types of NVM devices, such as NOR flash memory. For example, in ADAS design, developers can use NOR flash memory and Excelon F-RAM at the same time, the former is used to store firmware, and the latter can reliably handle multiple data streams from many automotive subsystems (providing input for ADAS applications) (Figure 4).

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 4: Automotive ADAS developers can combine Excelon F-RAM devices (used to store critical data) with NOR flash memory devices (usually used to store firmware or configuration data) in a microcontroller (MCU)-based design.

Developers only need to simply connect Excelon F-RAM to the serial peripheral interface (SPI) bus of the host processor to easily add it to the design. The CY15x102QN F-RAM is designed to be used as an SPI slave device, supporting SPI clock rates up to 50 megahertz (MHz). In a typical hardware configuration, the developer connects the serial input (SI) and serial output (SO) of the F-RAM to the master output slave input (MOSI) and master input slave output (MISO) lines of the SPI master, respectively . Then connect to the corresponding serial clock (SCK) and chip select (/CS) lines to complete the hardware interface. Developers can use multiple devices to share the host’s SPI bus (Figure 5).

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 5: Developers can use the shared SPI bus to connect the host processor with one or more CY15x102QN F-RAMs.

For MCUs without SPI function, the CY15x102QN device supports a simple alternative, which is to use the general-purpose IO (GPIO) of the microcontroller to emulate the SPI hardware interface to connect to the F-RAM. Developers only need to use three GPIOs to achieve this interface, that is, the SI and SO data lines of F-RAM use the same pin (Figure 6).

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 6: For the microcontroller without native SPI function, developers can simply use the general-purpose IO of the microcontroller to emulate the SPI protocol to access the CY15x102QN serial F-RAM.

In the standard SPI protocol, the master device initiates transaction processing by pulling down /CS. After /CS goes low, F-RAM interprets the next byte as an opcode. For example, the write operation corresponds to the SPI standard write operation code (02h), plus a three-byte address and some data bytes (Figure 7).

How to use F-RAM solutions to enhance the reliability of ADAS

Figure 7: Cypress’s CY15x102QN F-RAM device supports standard SPI opcodes and protocols. Developers can easily perform zero-latency write operations by sending the write opcode (02h), address, and data in sequence.

For 2 Mb CY15x102QN F-RAM, the address is a three-byte sequence, ignoring the upper six bits. Cypress recommends setting this high six bits to zero so that it can easily transition to higher capacity F-RAM devices in the future.

The read operation follows the same protocol. After receiving the standard read opcode (03h) and address, the F-RAM device sends data bytes sequentially through SO, automatically incrementing the memory address, and at the same time /CS remains low, and the clock signal continues to be generated. Therefore, developers can perform batch read operations, just keep /CS low and continue to send out the SCK clock signal until the required number of data bytes are read.

CY15x102QN F-RAM also supports a fast read function compatible with serial flash memory. After the fast read opcode (0Bh) and address, the SPI master sends a dummy byte to simulate the flash read delay. After receiving the dummy byte, F-RAM responds with the requested data. The fast read operation uses the same mechanism as the standard read operation, and batch read operations can also be performed.

Write protection

In addition to the SPI interface control logic, CY15x102QN F-RAM also provides other mechanisms to identify the device and write-protect the F-RAM array.

Developers can issue SPI opcodes to access the read-only unique ID and device ID of the CY15x102QN device, and obtain information such as manufacturer, memory density, and part version. Developers can also set an 8-byte read/write serial number register to associate F-RAM with a specific system or configuration.

Regarding F-RAM protection, the device provides both software and hardware mechanisms. For data protection in the manufacturing process, there is a dedicated 256-byte special sector that can maintain data integrity during up to three standard reflow soldering cycles. For protection during normal operation, the device uses a write enable latch (WEL) to protect the F-RAM array from accidental writes. When power is on, WEL is cleared by default, and the developer needs to issue the write enable (WREN) opcode (06h) to execute the write operation.

The device status register has a pair of block protection (BP) bits BP0 and BP1, allowing developers to protect the entire address range of the memory (BP1=1, BP0=1), or only the upper half of the memory (BP1=1, BP0=0) ), or only protect the upper quarter of the memory (BP1=0, BP0=1).

Developers can use the hardware write protection pin (/WP) to prevent software from modifying the BP bit during normal operation. To this end, the developer sets the write protection enable (WPEN) bit in the status register and sets the /WP pin to a low level to lock the status register.

Power management

When operating normally at a clock rate of up to 50 MHz, the inherent high energy efficiency of F-RAM technology makes CY15V102QN (VDD 1.71 to 1.89 V) a typical current consumption of only 5.0 milliamperes (mA). Developers can reduce the clock frequency to further save power, the current consumption of CY15V102QN at 1 MHz is reduced to about 0.4 mA. The current consumption of CY15B102QN (VDD 1.8 to 3.6 V) is only slightly higher, 6.0 mA at 50 MHz and 0.5 mA at 1 MHz.

When inactive for a long time, developers can use the SPI opcode to set the CY15x102QN device to one of the following three low-power modes, thereby significantly reducing power consumption:

In standby mode, the typical current consumption of CY15V102QN is 2.7 microamperes (μA), and that of CY15B102QN is 3.2 μA

Deep power saving mode, CY15V102QN is 1.1 μA, CY15B102QN is 1.3 μA

Sleep mode, 0.1 μA for both devices

As long as the SPI master sets /CS to high at the end of the opcode sequence, the CY15x102QN device will automatically switch to standby mode. To switch the device to deep power saving or sleep mode, the SPI master must use the SPI opcode protocol. Specifically, the steps for the SPI host to switch to one of the two lowest power consumption modes are as follows: first set /CS to low level, then send a special opcode (BAh for deep power saving, B9h for sleep), and finally /CS is set to high level (Figure 8).

Figure 8: The CY15x102QN F-RAM device automatically enters the standby mode after the opcode sequence ends, but developers can use the normal SPI opcode program to put it in a lower power consumption mode, such as deep power saving (DPD) mode.

When the SPI host sets /CS to high after sending the appropriate low-power opcode, the CY15x102QN F-RAM enters the required low-power mode within about 3 μs.

In standby mode, when /CS goes low, Cypress F-RAM will immediately return to active mode to start the next opcode sequence. In deep power saving or sleep mode, F-RAM will also return to active mode after /CS goes low, but there is a short delay of about 10 μs in deep power saving mode, and the delay time of sleep mode is 450 μs.


In a variety of applications that rely on more and more sensors to provide data, the demand for reliable, fast, low-power, and high-performance NVM has become more and more important. In mission-critical applications such as automotive ADAS, data loss can severely weaken the safety mechanisms designed to protect the vehicle and its passengers.

Using Cypress Semiconductor’s F-RAM devices, developers can easily add NVMs that can reliably store critical data for decades without sacrificing performance or low power requirements.

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