With the increasing diversification of upper-level application software, the functional requirements for embedded chips in current portable Electronic products are getting higher and higher, and traditional chips that can only be customized individually or locally can no longer meet the needs. Therefore, both digital systems and analog systems can be flexibly customized as needed to become the development direction of chip design and development. Cypress developed PSoC3 and PSoC5 new programmable analog and digital embedded chips after PSoC1 to meet the needs of the industry. Among them, PSoC3 uses a high-performance 8051 core (67MHz/33MIPS) based on a single-loop pipeline, and PSoC5 is a 32-bit ARM Cortex-M3 core (80MHz/100MIPS); both have built-in flash memory, SRAM, and support off-chip memory access. High integration and high flexibility are simultaneously achieved in 8, 16 and 32bit applications. This article focuses on the application of PSoC3 in the design of multiple communication interfaces, and how to use multiple DMA technology to improve the speed and efficiency of communication.
1. Introduction to Cypress PSoC3 Chip
Cypress PSoC3 uses a high-performance 8051 core (67MHz/33MIPS) based on a single-cycle pipeline, provides a voltage range of 5.5V to 0.5V and a sleep current as low as 200nA widely used in the industry, which can meet extremely low power consumption applications. Both the high-performance analog subsystem and digital system of PSoC3 have programmable channels, allowing any analog or digital signal (including programmable clock) to be distributed to any general-purpose I/O pin, which provides users with a true “system-level “Programmability.
The chip number of Cypress PSoC3 is CY8C38xx. This series of chips includes a variety of chips depending on the functional modules. Table 1 is the selection guide for the CY8C38xx series. In addition to the characteristics listed in the table, each CY8C38xx chip also contains: 1.024V±0.1% precision on-chip voltage reference source, 1~66MHz±1% precision voltage reference source with PLL Programming clock source, Flash with ECC (error correction code) function, DMA (direct memory access), 4KB RAM with debug tracking, JTAG/SWD programming/debugging interface, support for off-chip memory access, etc.
Cypress PSoC3 adopts the structure of CPLD to realize a complete digital programmable circuit. Figure 1 shows the programmable logic diagram inside the CY8C38xx series. As can be seen from Figure 1, peripherals and logic can be interconnected with each other or connected to any pin. Digital programmable logic includes the following parts.
UDB (Universal Digital Blocks) forms the core function of the programmable digital system, which is composed of PLD and Data
The path is composed to create various general peripherals and customized functions.
UDB Array is composed of multiple UDBs through matrix and programmable interconnection, and supports UDB and DSI (Digital System
Interconnect) is very flexible expansion.
DSI is a centralized interconnection of digital signals, including UDB, fixed-function peripherals, I/O, interrupts, DMA and other parts
Powerful analog resources and flexible analog wiring resources are also one of the highlights of PSoC3. Figure 2 is the on-chip analog resource diagram of the CY8C38 series of chips. These programmable analog circuits can form a standard analog signal processing module. And these analog resources can be connected through the internal analog interconnection subsystem, providing a high degree of freedom of analog design and protection of IP resources. The simulation subsystem has the following system composition.
·It has a highly configurable structure composed of analog global and local buses and analog switches.
High-precision Delta-Sigma ADC.
Support 8-bit voltage or current DAC.
Four comparators and can be selectively interconnected to LUT.
·Up to four SC/CT modules can form analog circuits such as OPAMP
·Up to four internal OPAMPs, which can be connected to GPIO as buffers for high current output.
· CapSense subsystem supports capacitive touch detection.
·Internal high-precision reference voltage source.
In addition to analog and digital programmable logic, the CY8C38 series of chips include a hardware accelerator DFB (Digital Filter Block) dedicated to digital filtering, and its internal dedicated multiplier and accelerator can calculate a 24-digit number within a system clock. Multiplication of 24 digits. Using DFB can easily implement FIR and IIR digital filters, and almost does not occupy MCU resources. In addition to implementing filters, DFB can also be used as an algorithm accelerator for PSoC3, which can implement various digital algorithms conveniently and quickly without occupying PSoC3’s CPU resources.
Figure 3 is the block diagram of the DFB module. A typical application is to connect the data of an on-chip data source (such as ADC or a DMA) to the DFB, and then output the result to another on-chip data source (such as DAC or DMA) after DFB processing. Another DMA). The data moving in and out can be set to be controlled by a specific DMA, or it can be moved directly by the MCU.
In addition to programmable resources, PSoC3 also provides modules with specific functions. These modules can complete the corresponding functions without occupying analog, digital programmable and MCU resources. These modules include:
·Support Can bus controller up to 1MBPS, compatible with ISO-11898-1 standard.
·Full-speed USB2.0 controller, supports 8 endpoints and DMA data transfer control.
· Support 50k/100k/400k/1M BPS I2C master/slave bus controller, compatible with Philips’The I2C
Specification’ Version 2.1.
·16 Bit dedicated timing, counting and PWM and other commonly used embedded system modules.
2. Cypress PSoC® Creator™ integrated development environment
Cypress PSoC Creator development environment is an efficient and easy-to-use inherited development environment provided by Cypress for PSoC3/PSoC5 programmable system-on-chip.
This unique new design software enables engineers to design according to their own way of thinking. Complete the design of programmable analog, digital and wiring resources based on circuit diagrams. The software also provides a unique embedded system component library to use its internal resources. By selecting components in the component library and using a circuit diagram-based method, the entire development process can be made like building blocks, which is simple and efficient to realize the engineer’s design. This software tool can automatically transform the user’s design into the configuration of the programmable circuit through circuit synthesis, so that the user can complete the complex circuit design even if the user does not know the details of the chip. When using PSoC Creator to design, customers are acutely designing based on application requirements, not the limitations of the target device. Rebuilding the design is like modifying the program, without complex board-level modifications.
PSoC Creator combines a latest software development IDE with a revolutionary graphic design editor to form a unique and powerful software and hardware synchronous design environment. It provides a rich content, with dozens of pre-configured analog and digital peripheral libraries, which can be easily dragged and dropped into the circuit diagram design interface to form a powerful system. The tool can also automatically assign pins for all on-chip signals, and even assign I/O to the best pins if necessary. The parameters of each peripheral component are carefully configured to ensure that the application effect can best meet the designer’s requirements, and there is no waste of resources. The build process produces a consistent and easy-to-remember API series for each component, so that software developers can control the hardware without worrying about basic execution instructions. Customized designs and related APIs can also be conveniently stored in the library for future projects or shared within the organization.
PSoC Creator includes a full-featured free compiler, and its unique integrated wiring tool can automatically synthesize customer design inputs and generate corresponding APIs. The PSoC3 project uses the Keil CA51 compiler commonly used in the industry, and the GNU GCC-ARM compiler is also included, which can compile for the PSoC5 design. After synthesis, compilation, etc. are completed, a configuration file compatible with Intel Hex format is generated to configure the chip.
The current version of PSoC Creator is: PSoC Creator 1.0 Production. The software running interface is shown in Figure 4.
The design entry PSoC Creator provides to users is as follows:
Schematic editor: This editor is the main tool for creating designs. Supports schematic editing of the design.
Text editor: This tool allows users to edit C, assembly, Verilog, C# and other language codes.
Design Resource Editor: This tool is used to configure the parameters of the entire design, including power supply, compilation switch, debugging switch,
Flash protection information, and pin assignments, etc.
Icon editor: allows users to create their own module icons
– Schematic Macro Editor: Allows users to set different macros on the schematic to complete different functions.
– Schematic template editor: allows users to edit the template of the schematic
– Icon Shape Editor: Allows users to use custom shapes in creating modules and schematics.
After the user completes the design through the design entry, PSoC Creator performs a series of processing on the design and completes the final result output. The construction process of this tool is shown in Figure 5.
As can be seen from Figure 5, the project construction process includes the following steps:
·Complete the design through the design input interface
·The synthesizer completes the synthesis of the circuit diagram, and performs layout, routing, mapping, etc.
The code generator generates the API control interface of the corresponding circuit
·The builder prepares the design source file, reads the build database, and obtains the build configuration, library files and other information
·The compiler completes the compilation, and the linker links the generated files
· Output configuration Hex file.
3. Cypress PSoC3 is applied to the DMA design of multiple communication interfaces
DMA is a module used in PSoC3 to handle fast data transfer. The DMA controller can handle data transmission without CPU intervention. Processing data transmission through DMA can effectively reduce the burden on the CPU, and it can also increase the data transmission time. PSoC3’s built-in DMA can complete four basic data transfers:
·Memory to memory
·Memory to peripheral
· Peripherals to memory
· Peripheral to Peripheral
In PSoC3, PHUB is used to connect various internal devices. Both DMA and CPU need to use PHUB to complete data transfer.
The two master devices on PHUB are DMA and CPU, and the slave devices are memory, peripherals, and control and configuration registers. PSoC3 supports multiple DMA channels, and the DMA master controller arbitrates the channel requests according to priority. A single DMA channel can transfer up to 64KB of data.
PSoC3’s DMA controller supports the following features:
· Support 24 DMA channels
·8 Priority decision
128 transaction descriptors
·8/16/32 bit data transmission
· Fully configurable source and destination addresses
·Compatible with different data terminals
Ability to generate interrupts after completing data transfer
·DMA wizard can accelerate DMA-based development
· DMA transaction can be triggered by programmable digital logic or CPU
Support the cascade of multiple DMA channels and descriptors to complete complex functions.
3.1 Use DMA in PSoC Creator
As a design tool developed for PSoC3 and PSoC5, PSoC Creator integrates a DMA module to configure DMA and generate related control codes. At the same time, it provides a DMA wizard to implement a graphical operation interface.
The DMA module is located in the System directory of the component window, as shown in the figure.
The DMA module can be placed by dragging it to the schematic editor, and each dragged DMA will use one channel. The input and output addresses of the DMA module need to be configured in the code, and what is configured through the schematic diagram is the control pin and control information. The performance of the DMA module on the schematic diagram is shown in Figure 7 below.
It has three input and output pins.
nrq-output pin. This command is used to characterize the completion of the DMA transfer, and is used to notify the interrupt controller to generate an interrupt or to trigger other logic. When the transfer is completed, the DMA will generate a 2 bus cycle pulse.
drq-input pin (optional). This pin is an optional pin, which is visible only when the trigger condition is selected as hardware.
This pin can be connected to the module that generates the DMA transaction request, and the trigger condition can be configured as level trigger or edge trigger.
trq-input pin (optional). This pin is optional and only visible when the end condition is selected as hardware.This pin
After the trigger, DMA will stop data transmission.
After configuring the hardware connection, use the configuration wizard to complete the configuration of the following parameters of DMA:
·Byte Per Burst-the number of bytes transmitted per burst transmission
·The number of Transaction Descriptor
·Endian (Big / Little) configuration
· Number of bytes transferred
·Address increment mode
·TD connection mode
Open the DMA wizard in PSoC Creator, select the DMA to be configured, and enter the first page as shown in Figure 8.
This interface mainly configures the range of target and source addresses. Support address segment in SRAM, FLASH, EEPROM. The second is to configure the number of bytes of Burst and the number of transaction descriptors in the DMA and the connection relationship. After completing this step, you will enter the next configuration interface to configure other detailed parameters. As shown in Figure 9.
Figure 9 DMA detailed configuration
Enter the parameters of the transaction descriptor in Figure 9. The most commonly used and important parameters include: source address, destination address, address increment mode, and transaction descriptor connection mode. After completing this step, click Next, and the corresponding configuration code will be generated, as shown in Figure 10.
Figure 10 DMA generated code
Copy the above code to the initialization module of the program, and make subtle modifications where necessary to complete the initialization of the DMA. When the program is running, DMA will automatically move the data from the source address to the target address according to the request.
3.2 Examples of DMA applied to multiple communication ports
DMA data transmission can greatly improve the throughput rate of PSoC3-based systems. Take a system as an example. The system receives input from other systems via SPI and transmits it to the host system via UART. Figure 11 shows a comparison between the two program flowcharts based on traditional MCU and PSoC3 DMA (not considering the mismatch of the two transfer rates).
Figure 11 (a) Traditional MCU design (b) PSoC3 DMA design
The traditional MCU needs to initialize the SPI and UART communication modules and configure the interrupts of both. When the SPI buffer is full, an interrupt is generated. The interrupt program first suspends the new SPI transmission, and then checks the UART buffer. If it is not empty, wait for the old data to be transmitted. After it is empty, copy SPI data to TX Buffer and open SPI to receive subsequent data.
In the design based on PSoC3 DMA, the above-mentioned logic can be realized based on the schematic diagram. As shown in Figure 12.
When the Full signal of SPI and the Empty signal of UART are valid at the same time, the DMA transfer is triggered and the data in the SPI Buffer is transferred to the UART buffer. Data sharing between multiple communication ports can be completed without CPU intervention.
This communication example is just to show the role of DMA in the data transmission of multiple communication ports. In actual implementation, the communication ports that DMA can operate include:
· UART Buffer
·Buffer of SPI
· Various other custom communication protocols
The following operations between communication interfaces can be efficiently realized through DMA:
·Data transfer between communication ports
·Transmission between communication port Buffer and PSoC3 digital and analog modules
·Communication port Buffer is automatically stored in memory
·Data transfer from memory to communication port
·Data transfer from digital and analog modules to communication ports
Cypress PSoC3 processor integrates a variety of programmable digital and analog resources and wiring resources, as well as some dedicated communication and control equipment, which can greatly facilitate the application of various embedded systems. PSoC Creator, as a development tool for PSoC3, can provide design patterns based on schematics and functional components. Enable users to complete complex programmable system design in a simple and effective way.