Cypress’s CY8C38 series are ultra-low-power flash programmable system-on-chip (PSoC®) devices, which are part of the expandable 8-bit PSoC 3 and 32-bit PSoC 5 platforms. The CY8C38 series provides multiple configurable analog, digital and interconnect circuit modules around the CPU subsystem. By combining the CPU with highly flexible analog subsystems, digital subsystems, routing, and I/O, a high degree of integration can be achieved in many consumer, industrial, and medical applications. This article introduces the main features and block diagrams of the CY8C38 series, as well as the main features, circuit diagrams, bill of materials and PCB layout diagrams of the CY8CKIT-030 PSoC® 3 development kit.

With its unique configurable module array, PSoC® becomes a true system-level solution that provides microcontroller unit (MCU), memory, analog and digital peripheral functions in a single chip. The CY8C38 series provides a new type of signal acquisition, signal processing and control method, and has the characteristics of high precision, high bandwidth and high flexibility. Its analog function covers a wide signal range from thermocouple signals (close to DC voltage) to ultrasonic signals. The CY8C38 series can handle dozens of data acquisition channels and analog inputs on each general-purpose input/output (GPIO) pin. The CY8C38 series is also a high-performance configurable digital system. Some devices have interfaces such as USB, (I2C), and Controller Area Network (CAN). In addition to the communication interface, the CY8C38 series also has an easy-to-configure logic array, flexible routing to all I/O pins, and a high-performance single-cycle 8051 microprocessor core. With PSoC Creator ™, a hierarchical-based schematic design input tool, you can easily create system-level designs using a rich library of pre-built components and Boolean primitives. Using the CY8C38 series can not only realize the integration of analog and digital material tables, but also can easily incorporate the latest design changes through a simple firmware update.

Main features of CY8C38 series:

 Single cycle 8051 CPU

 Operating frequency is between DC and 67 MHz

 Multiplication and division instructions

 Up to 64KB flash program memory, 100,000 write cycles, 20-year retention time and multiple safety functions

 Up to 8 KB error correction code (ECC) or configuration flash memory

 Up to 8 KB of SRAM

 Up to 2 KB electrically erasable programmable read-only memory (EEPROM), 1 million write cycles and 20-year retention time

 24-channel direct memory access (DMA), multi-layer AHB[1] Bus access

• Programmable chained descriptor and priority

• Support high-bandwidth 32-bit transmission

 Low voltage, ultra-low power consumption

 Wide operating voltage range: 0.5 V to 5.5 V

 High-efficiency boost regulator (input 0.5V, output 1.8V-5.0V)

 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 48 MHz. Low power consumption modes include:

• 1 μA sleep mode, providing real-time clock and under-voltage detection (LVD) interrupt

• 200 nA sleep mode, RAM retains data

 Multifunctional I/O system

 28 to 72 I/O (62 GPIO, eight special input/output (SIO), two USBIO[2])
 Can be routed from any GPIO to any digital or analog peripheral

 LCD drive from any GPIO, up to 46 × 16 segments[2]

 Any GPIO supports CapSense® [3]

 1.2V to 5.5VI/O interface voltage, up to 4 voltage domains

 Any pin or port can be set to accept an independent maskable IRQ

 Schmitt Trigger Transistor-Transistor Logic (TTL) input

 Open collector mode high level / low level

 The state of the GPIO pins can be configured during power-on reset (POR)

 SIO has a current sink capability of 25 mA

 Digital peripherals

 20 to 24 Universal Digital Blocks (UDB) based on Programmable Logic Devices (PLD)

 Full CAN 2.0b RX buffer (16) and TX buffer (8)

 Full-speed (FS) USB 2.0 12 Mbps (using internal oscillator)

 Up to 4 16-bit configurable timers, counters and PWM modules
 Realize FIR and IIR filters

 Standard peripheral library

• 8, 16, 24 and 32-bit timers, counters and PWM

• SPI, UART, I2C

• Many other peripherals listed in the catalog

 Advanced peripheral library

• Cyclic Redundancy Check (CRC)

• Pseudo Random Sequence (PRS) generator

• Local Interconnect Network (LIN) bus 2.0

• Quadrature decoder

 Analog peripherals (1.71 V  VDDA  5.5 V)

 -40 ℃ to +85℃, the internal voltage reference is 1.024 V ± 0.1%

 Configurable Delta-Sigma ADC with 8 to 20-bit resolution

• Sampling rate up to 192 ksps

• Programmable gain stage: ×0.25 to ×16

• 12-bit mode, 192-ksps, 66-dB signal-to-noise ratio and distortion ratio (SINAD), ±1 bit INL/DNL

• 16-bit mode, 48 ksps, 84-dB SNR, ±2 digit INL, ±1 digit DNL

 Up to four 8-bit, 8-Msps IDAC or 1-Msps VDAC

 Four voltage comparators with a response time of 95 ns

 Up to four uncommitted operational amplifiers with a drive capacity of 25 mA

 Up to four configurable multifunctional analog modules.Configuration examples include programmable gain amplifier (PGA), transimpedance amplifier (TIA), mixer, and sample and hold

 CapSense support

 Programming, debugging and tracking

 JTAG (4-wire) interface, serial wire debug (SWD) (2-wire) interface, and single-wire browser (SWV) interface

 Eight address breakpoints and one data breakpoint

 4 KB instruction trace buffer

 Support bootloader programming through I2C, SPI, UART, USB and other interfaces

 High-precision programmable clock

 3 to 62 MHz internal oscillator covering the entire temperature and voltage range

 4 to 25 MHz crystal oscillator, capable of achieving crystal oscillator PPM accuracy

 Able to generate internal PLL clock up to 67 MHz

 32.768 kHz monitor crystal

 Low-power internal oscillators with frequencies of 1 kHz, 33 kHz and 100 kHz

 Temperature and packaging

 -40 ℃ to +85 ℃ industrial temperature

 48-pin SSOP, 48-pin QFN, 68-pin QFN and 100-pin TQFP packages are available. CY8C38 series of ultra-low power flash programmable system-on-chip (PSoC®) devices are expandable 8-bit PSoC 3 And part of the 32-bit PSoC 5 platform. The CY8C38 series provides multiple configurable analog, digital and interconnect circuit modules around the CPU subsystem. By combining the CPU with highly flexible analog subsystems, digital subsystems, routing, and I/O, a high degree of integration can be achieved in many consumer, industrial, and medical applications.

Cypress CY8CKIT-030 PSoC3 development plan
Figure 1. Simplified block diagram of the CY8C38 series

CY8CKIT-030 PSoC® 3 Development Kit

CY8CKIT-030 PSoC® 3 Development Kit allows you to develop precision analog and low-power designs using PSoC 3. You can design your own projects with PSoC Creator™ or alter the sample projects provided with this kit.

The CY8CKIT-030 PSoC 3 Development Kit is based on the PSoC 3 family of devices. PSoC 3 is a Programmable System-on-Chip™ platform for 8- and 16-bit applications. It combines precision analog and digital logic with a high- performance CPU. With PSoC, you can create the exact combination of peripherals and integrated proprietary IP to meet your application requirements.

The CY8CKIT-030 PSoC® 3 development kit includes:

■ Development board

■ Kit CD

■ Quick start guide

■ USB A to mini B cable

■ 3.3-V LCD module

The PSoC 3 Development Kit has the following sections:

■ Power supply system

■ Programming interface

■ USB communications

■ Boost convertor

■ PSoC 3 and related circuitry

■ 32-kHz crystal

■ 24-MHz crystal

■ Port E (analog performance port) and port D (CapSense® or generic port)

■ RS-232 communications interface

■ Prototyping area

■ Character LCD interface

■ CapSense buttons and sliders
Cypress CY8CKIT-030 PSoC3 development plan
Figure 2. Outline drawing of CY8CKIT-030 PSoC® 3 development board
Cypress CY8CKIT-030 PSoC3 development plan
Figure 3. CY8CKIT-030 PSoC® 3 development board circuit diagram
CY8CKIT-030 PSoC® 3 Development Board Bill of Materials:
Cypress CY8CKIT-030 PSoC3 development plan
Cypress CY8CKIT-030 PSoC3 development plan
Cypress CY8CKIT-030 PSoC3 development plan
Cypress CY8CKIT-030 PSoC3 development plan
Cypress CY8CKIT-030 PSoC3 development plan
Figure 4. PCB layout of CY8CKIT-030 PSoC® 3 development board: top layer

Figure 5. PCB layout of CY8CKIT-030 PSoC® 3 development board: bottom layer
For details, see:
http://www.cypress.com/?docID=35141
and
http://www.cypress.com/?docID=35957

The Links:   CLAA170EA02 LQ084V1DG44