This article discusses the application of Electronic system-level (ESL) design and verification methodologies to system-on-chip (SoC) design. ESL Design is a methodology that enables SoC design engineers to develop, optimize, and verify complex system architectures and embedded software in a tightly coupled fashion, and it also provides the basis for verification of downstream register transfer level (RTL) implementations. Many of the world’s leading systems and semiconductor companies have adopted ESL designs. They use ESL to develop software-rich multiprocessor devices that provide the advanced functionality and high performance necessary for the success of innovative end products.
Why China’s electronics industry will be interested in ESL? Because China’s leading electronics companies are going through a transformation that is critical to their competitiveness. By adopting a technological innovation strategy, China will become a pure intellectual property (IP) provider rather than a pure IP consumer. Those companies that own the intellectual property will hold the keys to the IP library.
To successfully execute innovation strategies, Chinese companies must adopt advanced design methodologies used by innovation leaders. ESL design is such a methodology. It has been adopted by many international systems and semiconductor companies. In China, Datang has taken the lead in adopting ESL design in the development of China’s 3G mobile phone technology – TD-SCDMA. Tsinghua University and some industrial cooperation units have also adopted ESL methodology to develop advanced terrestrial digital multimedia broadcasting applications.
Embedded Software Drives SoC Design
Figure 1 summarizes data from a survey of SoC design engineers by market research firm International Business Strategies. It shows that there are two main SoC design challenges – the workload associated with designing embedded software and hardware architecture increases dramatically as processes shrink, while the workload for hardware implementation (RTL design, synthesis, physical design, etc.) increases much less. Note that the embedded software mentioned in this survey is provided by semiconductor manufacturers, and this software does not include software developed by system manufacturers that differentiates end products.
Figure 1: As process nodes shrink, the primary design effort shifts from hardware implementation to designing embedded software and hardware architectures.
The significant change in the main design effort from hardware implementation to embedded software and hardware architecture shows that the chip has truly become an embedded system.
The increase in embedded software development effort is largely due to the growing number of wireless and multimedia standards (or one of them) that enable compatibility and interoperability between consumer products. Standards such as JPEG, MPEG, 3G, GSM/EDGE, IEEE 802.11/a/b/g WLAN, Bluetooth and UWB are all necessary for the commercial success of the modern electronics industry.
The increase in architecture development effort is primarily due to the need for SoCs to integrate and optimize the increasingly complex processing, memory resources, and communication protocols necessary to execute embedded software with the requisite performance. In fact, advanced SoCs now employ 3 or more microprocessors and 3 or more digital signal processors (DSPs). Even mainstream designs already contain one microprocessor and two DSPs, and it is common to have two microprocessors and two DSPs.
In other words, embedded software is now driving SoC design, and embedded software is critical to developing China’s own communications and media interoperability standards.
Why design with ESL
Industry-leading companies use ESL design because it enables design engineers early software development, fast design and derivative design, fast hardware verification, and fast hardware/software (HW/SW) verification. It also provides a functional test bed that can be used to verify that downstream RTL implementations conform to system specifications. In addition, ESL design tools can synthesize custom processors optimized for the application, as well as rapidly develop and implement advanced algorithms.
Start software development early: For a large software development task, it is necessary to start software development as early as possible, even if the degree of reuse of the original software is high.
Using the SystemC language-based ESL design methodology, SoC architects can generate a high-level model that simulates SoC behavior and, if desired, SoC cycle-accurate timing. This model, called the transaction-level model (TLM), enables software design engineers to start software development months before the RTL design or silicon prototype is complete.
1.Rapid Design and Derived Design
The ever-changing consumer market demands the constant introduction of “new and improved” products.Some improvements can be gained by reprogramming the SoC, but more
Software may require more hardware resources, so design engineers must employ methods that enable rapid hardware design and derivative designs.
The RTL platform was designed to reduce derivative design problems, and it does this by providing a pre-validated architecture for future designs. However, the difficulty of optimizing RTL architectures and integrating RTL IP to meet new market requirements can significantly slow down the design process. An unoptimized architecture can negatively impact performance and power consumption. Ultimately, design teams may be forced to forego functionality to meet performance and power goals.
TLM is applied at the function call and packet transport layers. This is an abstraction layer where “design intent” is captured and which provides the design engineer with a direct and clear view of system behavior. The SystemC TLM model of the silicon IP is easily integrated into the TLM of the SoC architecture, which enables SoC architects to quickly research and analyze multiple alternative hardware architectures and hardware/software partitioning schemes (each with different performance and economical compromise) to determine the best architecture. This approach significantly speeds up the initial design, but its greatest benefit is the use of the original SoC TLM as an easy-to-change platform in rapidly changing derivative designs. TI adopted this approach to develop the OMAP family of processors and modems.
The level of abstraction of TLM is significantly higher than that of RTL, and it describes the circuit state within the module, the transitions accurate to nanoseconds, and the bus behavior to the exact point. As a result, leading companies such as STMicroelectronics believe that using cycle-accurate TLM will enable hardware verification and hardware/software co-verification 1,000 times or more faster than using RTL. Not only does this approach produce functional testbenches for validating system behavior and RTL implementations, it also supports co-simulation of SystemC and RTL so that the SoC TLM can be used as a “testbench” when downstream RTL implementation modules When available, they can be verified on this test bench.
Qualcomm’s experience shows that system-level HW/SW co-verification is better than C/RTL implementation-level HW/SW co-verification. A Viterbi decoder design can execute a packet in 20ms, but it takes 6 hours to simulate at the C/RTL level, Qualcomm estimates that 1,000 packets must be simulated to achieve reasonable confidence, so a total of 6,000 hours of simulation time, but this is not realistic. Co-validation of 1,000 packets with a TLM would take 6 hours, or less.
Synthesis of Application-Optimized Processors: Growing Processing Power Demands
This is often met by employing additional standard general-purpose (GP) processor cores. However, GP cores are built to address a wide range of applications, which may not be able to execute a given software algorithm with the necessary performance and may consume too much die area and power. In addition, it usually has to pay a lot of additional IP licensing fees and royalties.
This problem can be solved with an instruction set (IS) processor that is optimized for the needs of the application. A custom IS processor provides the necessary performance with only the absolutely necessary hardware resources. Using ESL tools, such processors can automatically synthesize starting from a structural description or custom IS itself. ESL tools also automatically generate software development tools for the processor, such as instruction set emulators, assemblers, linkers, disassemblers, debuggers, and C compilers.
In the case of Infineon, the company reportedly developed a netlist and development tools for an application-specific multi-rate DSP within two months.
3.Advanced Algorithm Development
Many advanced algorithms such as JPEG and MPEG used in consumer devices are digital signal processing algorithms that must be implemented to achieve performance and power consumption goals that may vary from device to device. Advanced algorithms are usually first designed as reference algorithms in floating-point arithmetic form (indeed, standard algorithms like JPEG and MPEG are generally implemented in this form), and then converted to fixed-point arithmetic form, embedded software and RTL implementations are Derived from the fixed-point arithmetic form.
Graphical ESL design and simulation tools for DSP algorithms enable this flow. For communications and multimedia applications, algorithm development can be accelerated with a pre-designed library of customizable DSP algorithms. There are also standard algorithm libraries such as 3G W-CDMA, GSM/EDGE, IS-95 CDMA, IEEE 802.11/a/b/g Wireless Local Area Network (WLAN), Bluetooth and UWB. When HW/SW is split, the use of microarchitecture libraries can speed up the development of RTL implementations. Datang used such tools to develop the baseband library of TD-SCDMA in cooperation with other companies.
TLM is a virtual integration platform that enables early-start software development, ESL design, and verification tasks. Figure 2 shows the centrality of TLM in SoC design.
Figure 2: ESL design and verification tasks.
The SoC TLM is essentially a network model of device resources without implementation details. The behavioral models of functional modules are built according to their input stimuli and output responses. Modules communicate through a bus or set of buses connected to each module by an API, and these communication processes are modeled as data flow mechanisms with associated data transfers. This avoids unnecessary implementation details that would obscure the design engineer’s view of system behavior and slow down simulations. The separation of module behavior from communication enables rapid modification or replacement of functional modules without redesigning the bus, and vice versa, it is also critical for fast IP integration and complex “what if” analysis.
There are three common TLM usage patterns: Programmer View (PV), Architect View (AV), and Verification View (VV). Although these modes represent three different views of the system, most models can be configured in all three modes.
Programmer’s View TLM is a functionally correct model of SoC that allows the use of legacy software and the early development of new software. In general, a PV TLM consists of functional models of the processor, memory, peripherals, and routers that direct transactions to the correct memory or peripheral (see Figure 3).
Figure 3: Programmer View TLM.
PV enables software developers to access necessary system resources and attributes, such as register visibility, register accuracy, and interrupt handling, while it also links directly to the target processor and the debug environment’s Instruction Set Simulator (ISS). The API of the target RTOS and the compiler of the target processor are used to develop the software object code. The application software development at this stage only needs a data flow schema (schema). Therefore, PV is untimed and PV simulation performs well in the speed range of millions of instructions per second.
Architect view TLM is the same model with SoC timing properties. The model enables design teams to analyze SoC performance to pinpoint bottlenecks before the design is implemented (see Figure 4). The final hardware/software split decision is made in this view.
Figure 4: Architect View TLM.
Timing is captured either explicitly or implicitly. Explicit timing can approximate the hardware performance of the SoC, expressed as a function of system events and event synchronization, while the internal timing of the module can be very precise.
Implicit timing models use timing annotations embedded in TLM API calls, so timing annotations are independent of functionality. This allows for rapid modification and performance characterization of candidate architectures and implementations for various functional blocks, and it also increases simulation speed, allowing implicit timing models to outperform explicit timing models.
The command-accurate ISS can be linked to an architectural view via the PV-AV transaction device, allowing analysis of system performance while executing software. The PV-AV Transaction Server can also evaluate the architecture of the application executing in the Operating System (OS). The OS boots in PV mode, and the application executes in AV mode.
3. Verify View TLM
The Verification View is essentially the AV model enhanced with cycle-accurate timing. This model enables hardware verification and hardware/software verification that accurately predicts real chip timing, and it also enables development teams to create test benchmarks for RTL verification. Once completed, the RTL model written in Verilog and/or VHDL can be instantiated in the VV TLM model, allowing system verification and debugging before the full SoC implementation model is complete.
The execution speed of VV simulation is generally three orders of magnitude faster than that of RTL simulation and C/RTL HW/SW co-verification.
These three TLM views make up the overall ESL design flow (shown in Figure 5), and different models can be executed collaboratively using easy-to-design processors and converters.
Figure 5: HW/SW development flow with three main TLM usage models.
ESL Design Success Stories
Leading systems and semiconductor companies, which have publicly claimed that ESL designs have exceeded expectations, have turned to standard operating procedures for developing software on quasi-silicon multiprocessor system simulation models that execute with near real-time performance. In some cases, the simulation model boots a normal RTOS, such as embedded Linux, in as little as two seconds. The TLM method has good accuracy, which is critical for optimizing the performance and power consumption of the chip architecture before the silicon prototype is delivered to manufacture.
For example, a large Japanese printer company adopted an ESL design approach because the RTL-based approach could no longer cope with the significant architectural modifications required for each generation of printers. The company uses the same basic algorithm for everything from low-end home printers to high-end network printers. However, significant differences in data communication, processing, and storage requirements for different printer types require significantly different implementations of those algorithms, including different memory architectures and communication bus architectures.
Optimizing these different architectures can only be efficiently achieved at the level of TLM abstraction provided by the ESL design. However, simply moving to an ESL design without a link to an RTL implementation will cause downstream problems. The company uses pin-accurate transactions to establish this link that allows SystemC TLM to co-verify with RTL.
Moving from RTL to ESL design is a good transfer path. ESL is a “middle-out” design flow that allows reuse of legacy RTL IP. In those cases where there are no traditional constraints, a “top-down” design flow can be employed. Toshiba used this process to develop a user-configurable media embedded processor (MeP) using a design kit. The foundation of this design kit is an ESL design environment that enables design engineers to customize configurations for specific applications. Design engineers can study different configurations to determine which one is best, and they must verify not only the architecture, but also whether each hardware and software module meets the system requirements.
LSI Logic takes a similar approach in its ZSP digital signal processor core design. LSI has an accurate SystemC model for each different core development cycle and transaction, which enables design engineers to model core performance in the SoC architecture. These models also enable design engineers to debug hardware-software interactions. In addition, designers can analyze processor throughput and latency as well as memory performance.
Summary of this article
The ESL design and verification methodology enables design engineers to focus on those system design attributes that bring differentiation and value to products and IP, namely functionality and performance. These properties are determined by advanced algorithms, complex multiprocessor and memory architectures, advanced communication protocols, and application-optimized processors (all driven by embedded software). The sophistication of an RTL implementation is related to an efficient implementation, but its value resides in the system design. The innovation and ownership of IP will become the next revolution in China’s electronics industry, and ESL design and verification methodology will become the supporting force for this revolution.